The present invention relates to a comparator bank of an A/D (analog-to-digital) converter.
A conventional 8-bit flash A/D converter is shown in FIG. 2. FIG. 3 is a view showing the comparator bank of the A/D converter, which is folded back into four rows in this example. In the figures, letters A, B, C and D indicate the individual comparator rows, and numerals 1 and 64, numerals 65 and 128, numerals 129 and 192 and numerals 193 and 256 indicate comparators which lie at both the ends of the corresponding comparator rows. Letter L in FIG. 2 denotes the layout of ladder resistors which constitute a ladder circuit for supplying the respective comparators with reference tap voltages. That is, a predetermined reference voltage is divided, and the resulting reference tap voltage are applied to the comparators 1-256 in the order of lower voltages. In addition, symbols GND and VDD denote the layouts of a ground line and a supply voltage line which form feeder lines to the individual comparators, respectively.
In the A/D converter thus constructed, all the comparators simultaneously compare an input voltage with the reference tap voltages produced by the ladder circuit L, and the results are used for generating a converted digital code.
A similar A/D converter is of the CMOS type and disclosed in an article entitled "WAM 2.7: CMOS 8b 25 MHz Flash ADC," by Tsukada et al, Published in IEEE, ISSCC Digest, 1985.
As shown in FIG. 2, the prior-art A/D converter has the following problem. Since the ground line GND and the supply voltage line VDD are branched at the folded-back parts of the comparator bank, the potential distribution of the comparators becomes irregular. The individual comparators operated with the irregular potentials exhibit characteristics different from one another, and especially, the characteristics are greatly different between the comparators adjoining at the folded-back parts of the comparator bank (between, for example, the adjacent comparators 64 and 65, 128 and 129, and 192 and 193). In consequence, the linearity of the A/D converter is impaired as a whole.